The present invention relates to semiconductor device manufacturing techniques, specifically fabrication of through silicon vias (TSVs) with multiple diameters.
In the microelectronics industry, packaging density continuously increases in order to accommodate more electronic devices into a package. In this regard, three-dimensional (3D) stacking technology of wafers and/or chips substantially contributes to the device integration process. Typically, a semiconductor wafer includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, etc.) built on a silicon substrate. A wafer may be cut into a number of portions to define chips. A top layer of such a chip may be connected to a bottom layer of another such chip by means of through silicon interconnects or vias. In order to form a 3D integrated circuit (IC) stack, two or more chips or wafers are placed on top of one other and bonded.
Previous methods for electrically connecting the stacked chips or wafers used vias that consumed geometric space on the 3D IC by connecting multiple vias of a single diameter utilizing additional wiring levels. The formation of TSVs with complex shapes, such as multiple diameters in a single TSV, has used inefficient fabrication methods utilizing additional mask layers and patterning steps, which adds cost, complexity, and process time to the manufacturing process.
3D wafer stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, and greater integration through system-on-chip (SOC) solutions. In addition, the 3D wafer stacking technology may provide other functionality to the chip. For instance, after being formed, the 3D wafer stack may be diced into stacked dies or chips, with each stacked chip having multiple tiers (i.e., layers) of integrated circuitry. SOC architectures formed by 3D wafer stacking can enable high bandwidth connectivity of products such as, for example, logic circuitry and dynamic random access memory (DRAM), that otherwise have incompatible process flows. At present, there are many applications for 3D wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, and other SOC solutions.